1. Field of the Invention
This invention relates to a printed circuit board (PCB) and more particularly to a land formed upon the PCB having an inwardly facing surface, and a controlled thickness of solder placed upon at least a portion of the inwardly facing surface. During placement, the solder covered surface is configured to channel a surface mount component (SMC) lead to a middle portion of the land.
2. Background of the Relevant Art
PCBs or printed wiring boards (PWBs) are rigid or flexible, single, double or multi-layered boards having printed conductors placed upon or within the board material. A PCB is designed to receive separately manufactured electrical components and to interconnect those components into an overall circuit structure. The components comprise integrated or discrete circuits well known in the semiconductor art.
PCBs are manufactured by subtractive or additive processes from rigid copper-clad, epoxy-impregnated glass fiber laminate or phenolic-impregnated paper. Regardless of the base material used or the process by which printed conductors are formed, the desired outcome of PCB manufacture remains the same: to produce a dielectric structure having densely patterned printed wires arranged upon the dielectric outer surface or at one or more layers within the dielectric. The resulting overall structure provides a reliable mechanical and electrical support for components arranged thereon.
The technology used in forming a PCB as well as the packaged component arranged thereon has evolved over time. Initially, most components were packaged in large metal, glass and/or plastic material having sparsely spaced, thick (large cross-sectional) leads extending from the package material. To accommodate the thick, sparsely spaced leads, sockets or metal eyelets were fashioned within the PCB in registry with the leads. The thick leads and accommodating eyelets/sockets have given way to some extent to more densely spaced interconnect schemes.
Recent advances in integrated circuit fabrication have brought about packaged components having a hundred or more leads extending from the package. In order to place numerous components and connect dense leads from those components to the PCB, advances in interconnect are necessary. One such advancement involves the use of plated-through holes (PTHs) arranged upon the PCB. PTHs are patterned at small pitch distances across the PCB in registry with densely spaced, smaller cross-sectional leads. PTHs require a hole formed at least partially through the PCB with conductive plating deposited on the walls of the holes. The plated hole is covered with a solder material such that, during wave soldering or reflow, molten solder is drawn up around leads placed in the holes by capillary action to form a secure bond. PTHs are easier and less costly to form than metal eyelets and can receive thinner leads of lesser pitch. Accordingly, PTHs allow miniaturization of component-to-PCB interconnect.
More recently, PTH techniques have, in some respects, given way to an even more dense interconnect scheme often referred to as surface mount technology. Instead of drilling holes through the PCB and placing component leads through plated holes, surface mount "lands" are formed on the PCB surface only, and are configured to receive leads from a surface mount component (SMC). While PTH leads are smaller than leads inserted into metal eyelets or sockets, PTH leads must nonetheless be large enough to withstand the rigors of insertion. Since they need not be inserted into a hole, surface mount leads can be made much thinner then PTH leads and can therefore be placed at an even lesser pitch.
Compared to an equivalent PTH PCB, a typical surface mount PCB can be made 20 to 50 percent smaller. Most of the savings associated with manufacturing a surface mount PCB can be attributed directly to its smaller physical size. Additional cost savings arise from not having to drill the PCB and plate the inside surface of the drilled hole. A surface mount PCB also achieves a high frequency performance advantage over PTH PCBs. Not having to extend through a hole, surface mount leads are much shorter than PTH leads and therefore avoid added parasitic inductances and capacitances associated with longer leads.
In general, SMCs can be classified according to various lead configurations. SMCs can be either leaded or leadless. Leadless SMCs generally embody the lead as an exposed part of the edge or backside surface of the packaging material. A metalized material comprising the lead is formed generally flush with or slightly raised from the outer surface of the leadless package. Leadless SMCs which package an integrated circuit have often been referred to as leadless chip carriers. While leadless chip carriers allow shorter leads than leaded SMCs, leadless chip carriers nonetheless suffer from thermal mismatch at the interconnect joint during reflow soldering and operation. For example, ceramic of a leadless ceramic chip carrier has a considerably lower coefficient of thermal expansion (CTE) than counterpart leaded SMCs or leaded chip carriers. Instead of the interconnect joint being in direct thermal contact with the package material, leads of a leaded SMC are displaced from the package material to allow thermal matching to lands upon the PCB. If the leads are configured directly upon or embedded within the package, as in the leadless variety, then thermal stress during solder reflow and thermal energy generated from the package during operation may cause failure at the interconnect joint.
Leaded SMCs have risen in popularity as an alternative to leadless SMCs partly due to CTE problems associated with leadless SMCs. The leads of a leaded SMC are generally classified in three groups: gull-wing, j-bend and i-lead arrangements. Small-outline SMCs, tape carrier SMCs leaded chip carrier SMCs and quadpack SMCs all utilize various gull-wing, j-bend and i-lead arrangements.
Not only do leaded SMCs overcome CTE problems of leadless SMCs, but can in some instances achieve a thinner lead of lesser pitch than leadless SMCs. Leads from, for example, a quadpack or a tape carrier package can achieve pitch distances of approximately 0.02 in. Densely patterned leads make leaded SMCs well suited for large integrated circuits having a hundred or more leads such as microprocessors or microcontrollers. However, to achieve the necessary pitch density, the lead frame must be manufactured from thin metal stock, making the leads extremely fragile. The thin leads with fine pitch distances therebetween are often bent or deformed during handling. When placed upon the PCB, the bent or mishandled leads may not come in registry with their respective lands. Additionally, the thin leads can readily flex or bend when placed upon respective lands.
After the leads are brought in contact with lands and during reflow operation, the thin leads can further move from the desired (or placed) position. Surface tension of the molten solder can readily pull a thin lead of a leaded SMCs to a position of minimum solder surface energy. If the land is poorly designed and solder placed on the land surface is not formed at a controlled thickness, then solder surface energy gradient may exist which forces molten solder to carry the lead from the land position to a position near the edge of the land or completely off the land.
Movement of a lead from the land, caused either by physical contact of the lead to the land or subsequent reflow, will result in an open circuit at the interconnect position. Additionally, if two leads are misaligned and directed toward one another, a short circuit will occur. It is therefore important to improve placement accuracy of lead-to-land interconnect, not only during placement but also during subsequent solder reflow.